Power analysis and implementation of a low-power 300 MHz 8-b × 8-b pipelined multiplier
نویسندگان
چکیده
This paper analyzes the power consumption of an array pipelined multiplier. To precisely realize a low power pipelined multiplier, the analytical model for a clocking system is presented. Simulation results show that the storage element is the key-component in a high performance pipelined multiplier macro. Compared with the conventional DFF and latch, the new low power DFF as PTTFF [6] achieves total power reduction ranging between 34 and 62 percents in a pipelined multiplier macro.
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